Si/Ge/GaAs as channel material in nanowire-FET structures for future semiconductor devices

In nano-scaled devices, as the voltage is scaled down in order to achieve low power which further causes the threshold voltage also to be scaled in order to meet the performance requirements. However, reduction in threshold voltage leads to increased leakage power in short channel devices. Nanowire FET (NW-FET) is a possible alternative to minimize short channel effects in traditional MOS structure. In this paper we have justified the advantage of naowire FET over MOSFET by varying oxide thickness. Then we have seen the impact of channel length over characteristics of NW-FET with Si, Ge and GaAs as channel materials. With nanoHUB simulation, we found that, while reducing the channel length from 12 nm to 4 nm, the drain current and subthreshold swing (SS) at a very small Vg increases due to tunnelling effect. In NW-FET, the drain current is normalized by the circumference of the nanowire and the SS is defined as the inverse of the slope of log₁₀ Id vs Vg curve. We have also simulated and analyzed that the electron density at channel region while reducing the channel length.