Multitime programmable (MTP) memory cell with pseudo differential architecture

A multitime programmable (MTP) memory cell based on pseudo differential architecture is presented in this paper. The proposed cell has only one floating gate, it takes advantage of the opposite polarity of PMOS transistor and NMOS transistor to output differential reading currents. The new cell has the same data retention capability as the state-of-the-art differential cell. Furthermore, it saves about 58% of the cell area with respect to the conventional differential cell. A test chip is fabricated by using a 0.13 μm standard CMOS process, and extensive experimental results are provided.