A 15Gb/s wireline repeater in 65nm CMOS technology

This paper describes the design of a wireline repeater in 65nm CMOS technology. The T-coil networks with ESD protection are used in both repeater´s input and output to realize impendence matching and bandwidth enhancement. Three continuous time linear equalizers (CTLE) placed in the data path are used to compensate for high frequencies loss, while the current mode logic (CML) buffer chain is used to compensate for DC loss. The measurement results show that the repeater could deliver 15 Gb/s data through a 10 inch channel which has a 19.2 dB loss at 7.5GHz. The power consumption is 2.67mW/Gbps under 1.1V supply voltage and the chip area is 0.63mm².