Write ability enhancement techniques for L1 cache on next-generation IBM POWERTM processors

In this paper, two write ability enhancement techniques are presented for the L1 data cache on next-generation IBM POWER^TM processors. Write ability is improved by 15.1% at 1.2V with V_DD lowering technique for a dual-ported 6T bitcell with a beta ratio of 4. Write ability is improved by 21.6% at 1.2V by using a dual-port dual-ended transmission gate bitcell with a beta ratio of 4. These numbers reduce to 11.8% and 17.1% respectively at 0.7V. The enhancement in bitcell write ability is achieved with the inclusion of additional control logic per word, and by trading off bitcell area and leakage currents.