Layout optimized non-uniform series-parallel inductors for high inductance density and quality factor

High resistivity, silicon-on-insulator CMOS technologies allow the usage of lower metals to build miniaturized 3D inductors due to reduced substrate losses. Compact and layout optimized 3D series stacked inductor structures with high quality factor (Q) and increased current handling capability are proposed in this paper. The bottom-most spiral in the series stack is realized using multiple via connected layers to simultaneously increase Q and current handling capability. Increased width and reduced spacing at the bottom metals is shown to be useful for improved inductor performance. Measurements show significant improvements in inductance density, quality factor and current handling using the proposed inductors.