Title :
On the breakdown physics of trench-gate drain extended NMOS
Author :
Ketankumar H. Tailor;Mayank Shrivastava;Harald Gossner;Maryam Shojaei Baghini;V. Ramgopal Rao
Author_Institution :
Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India
fDate :
6/1/2015 12:00:00 AM
Abstract :
In this work, two drain extended NMOS (DeNMOS) devices, one with only planar gate and another with both planar gate and gate in a trench under the gate-drain overlap region (called trench-gate DeNMOS) are investigated. The latter device shows improved ON-state performance due to greater space-charge control with addition of trench gate. The OFF-state breakdown physics is also compared with conventional DeNMOS device. Due to greater field spreading in the trench-gate device under OFF-state conditions, a distinct base-push effect is not observed, unlike conventional device. The oxide reliability in trench-gate device improves with an additional offset in the drift region. Therefore, the trench-gate DeNMOS can be used as an alternative to improve input/output (I/O) device performance and reliability in advanced system-on-chip (SoC) applications.
Keywords :
"Logic gates","Electric breakdown","Junctions","Performance evaluation","Physics","Semiconductor process modeling","Impact ionization"
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2015 IEEE International Conference on
Print_ISBN :
978-1-4799-8362-9
DOI :
10.1109/EDSSC.2015.7285240
