Towards ultra low-power MCU implementation through physical design based on improved multibit SRPG

This paper presents a physical design for ultra-low power MCU usage based on improved multibit SRPG process. The State Retention Power Gating (SRPG) is used to save static power when the chip turns to sleep mode and its area occupies 50% of the whole standard cells area. The existed multibit SRPG cells occupy too many high metal layers, which lower the utilization of the standard cell region. In this paper, we tuned the layout of the SRPG cells, drastically reduced the number of the high metal. The degree of optimization depends on the experience. Designing the 4bit SRPG based on the 2-bit SRPG is another important task. And the 4-bit SRPG will be designed to 4-row height comparing with the original one with 2-row height, consequently reducing the width of the layout. After the layout is completed, we extract the LEF file of the SRPG and rerun the synthesis and physical design process. The results turn out that the global area of the die can be reduced 2.3%.