DocumentCode :
3667131
Title :
Implications of inelastic tunneling on the depth of oxide traps in MOSFETs assessed by RTS or BTI
Author :
E. Simoen;C. Claeys;W. Fang;J. Luo;C. Zhao
Author_Institution :
Imec, Kapeldreef 75, B-3001 Leuven, Belgium
fYear :
2015
fDate :
6/1/2015 12:00:00 AM
Firstpage :
1
Lastpage :
4
Abstract :
The impact of inelastic tunneling on the interpretation of flicker noise spectra and Bias Temperature Instability relaxation will be discussed in terms of a simple man´s model. The impact of various parameters, like the barrier for capture or the relative position of the Fermi level with respect to the trap level is investigated for the Si/SiO2 system. Overall, it is derived that the extracted trap depth is smaller than in the assumption of purely elastic tunneling. For larger (de)-trapping time constants, like in the case of BTI, traps at or nearby the interface correspond with deep capture barriers, while in the case of noise spectra, the range of possible defect parameters is more limited.
Keywords :
"Tunneling","Logic gates","Electron traps","Noise","MOSFET circuits","MOSFET","Silicon"
Publisher :
ieee
Conference_Titel :
Noise and Fluctuations (ICNF), 2015 International Conference on
Type :
conf
DOI :
10.1109/ICNF.2015.7288543
Filename :
7288543
Link To Document :
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