Mechanical simulation of stress engineering solutions in highly strained p-type FDSOI MOSFETs for 14-nm node and beyond

Stress engineering is a powerful tool to enhance nanoscale device performances. In this study we developed a methodology of 14nm strained pMOS FDSOI device mechanical simulation in order to carefully evaluate different stress effects on device performances. Mechanical simulation results are presented for different process solutions, such as Gate-First (GF) and Gate-Last (GL) processes but also for variation of germanium contents in source/drain and channel regions.