Leakage reduction in stacked sub-10nm double-gate MOSFETs

In this paper, the effectiveness of transistor stacking (or supply-gating) to reduce the leakage in the standby-mode of operation of sub-10nm double-gate MOSFETs is investigated. For that purpose, device parameters such as symmetric/asymmetric gate-to-source/drain underlap and body thickness are optimized to improve the ON-state current to the OFF-state current ratio. The optimized devices are then used in circuit simulation to analyze the dependence of each major leakage source (direct source-to-drain tunneling, thermionic, and gate oxide leakage currents) on the device geometry (t_si and symmetry in L_UN) and input vectors for two- and three-stacked transistors. The analysis shows that supply-gating is effective in reducing direct source-to-drain current as well as thermionic leakage in the stand-by mode of operation for sub-10nm technology.