Layout-induced stress effects on the performance and variation of FinFETs

Recently, LLEs(Local Layout Effects) and their impact on performance due to STI stressor and eSiGe S/D have been reported in FinFETs[1]. However, the impacts of gate and contact stress are rarely demonstrated. In this paper, we extended the LLE factors to the gate and contact and analyzed their impact on the electrical parameters of mobility, IdSat and VtSat via TCAD simulation study. This work shows that 5(20)% of n(p)FET performance enhancement and only 1(2)% of IdSat variation can be obtained through optimal stress components aligned with LLE factors.