TCAD analysis of FinFET stress engineering for CMOS technology scaling

In this paper, we analyze the mechanical stress induced from source/drain embedded SiGe (eSiGe) in multiple generations of FinFET technologies. By leveraging TCAD simulations, we show that high stress over the entire fin height could be achieved with a proper design of the eSiGe cavity. We also find that the stress should not undergo any reduction as the industry continues to scale down CMOS technologies. Hence, it should still play a major role in boosting semiconductor device performance for the next generation of FinFETs.