Hardware implementation design of analog neural rank-order filter

Hardware implementation design in FPGA based reconfigurable computing architecture of analog neural rank-order filter is presented. The problem of rank-order filtering is solved on the base of analog neural circuit which determines maximal value signals among signal set. The filter is described by system of algebra-differential equations and combines such properties as high accuracy and speed, low computational and hardware implementation complexity, and independency on initial conditions. The filter can be used for processing of constant signals, variable signals, and also equal signals. The filter simulation examples confirming theoretical statements are provided. According to simulation results, the neural rank-order filter implemented in hardware is capable to signal processing with much higher speed comparatively to its software implementation.