Low-Cost Fault Localization and Error Correction for a Signed Digit Adder Design Utilizing the Self-Dual Concept

This paper details a low-cost fault localization and error correction technique for binary signed-digit adders that utilizes the self-dual concept. This new design approach will result in a higher reliability, i.e., 100% of the single stuck-at faults can be corrected. Our technique is based on the observation that the proposed method under the existence of any single stuck-at fault, when fed by the complement of its functional input, yields the fault-free complement of the desired output. First, we apply parity-based error detection modules. Upon detection of a fault, this is followed by input inversion, re-computation, and suitable output inversion. By comparing the faulty and fault-free outputs, we can localize the faulty component. The proposed approach has higher reliability and lower complexity compared to previous related works.