Affine Coordinate Binary Edwards Curve Scalar Multiplier with Side Channel Attack Resistance

Taking into account the high regularity and completeness of Binary Edwards Curves (BEC), BEC point operation efficient implementation in hardware becomes a need especially since such curves tend to be more resistant against side channel attacks than the classical Weierstrass Elliptic Curves. However, BECs require more GF(2k) operations for a single scalar multiplication. This constitutes a deterring factor for their wide adoption and standardization. In this paper, a design methodology, hardware architecture and implementation is proposed on the efficient implementation of BEC scalar multiplication accelerators. To achieve that, a parallelism approach is introduced on affine coordinate representation BECs supporting fast GF(2k) inversion through a GF(2k) inversion algorithm capable of realizing also GF(2k) multiplication. The resulting architecture using 4 parallel operating GF(2k) arithmetic units when implemented in FPGA technology provide better results than similar Weierstrass Curves following parallelism techniques, indicated that BECs support parallelism better than their Weierstrass equivalent.