DocumentCode :
3674771
Title :
A Many-Core Co-Processor for Embedded Parallel Computing on FPGA
Author :
José;Horácio ;Mário Véstias
Author_Institution :
Inst. Super. Tocnico, Univ. de Lisboa, Lisbon, Portugal
fYear :
2015
Firstpage :
539
Lastpage :
542
Abstract :
Single processor architectures are unable to provide the required performance of high performance embedded systems. Parallel processing based on general-purpose processors can achieve these performances with a considerable increase of required resources. However, in many cases, simplified optimized parallel cores can be used instead of general-purpose processors achieving better performance at lower resource utilization. In this paper, we propose a configurable many-core architecture to serve as a co-processor for high-performance embedded computing on Field-Programmable Gate Arrays. The architecture consists of an array of configurable simple cores with support for floating-point operations interconnected with a configurable interconnection network. For each core it is possible to configure the size of the internal memory, the supported operations and number of interfacing ports. The architecture was tested in a ZYNQ-7020 FPGA in the execution of several parallel algorithms. The results show that the proposed many-core architecture achieves better performance than that achieved with a parallel generalpurpose processor and that up to 32 floating-point cores can be implemented in a ZYNQ-7020 SoC FPGA.
Keywords :
"Field programmable gate arrays","Algorithm design and analysis","Process control","Arrays","Computational modeling","Embedded systems"
Publisher :
ieee
Conference_Titel :
Digital System Design (DSD), 2015 Euromicro Conference on
Type :
conf
DOI :
10.1109/DSD.2015.23
Filename :
7302321
Link To Document :
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