CLEFIA Implementation with Full Key Expansion

In this paper a compact and high throughput hardware structure is proposed allowing for the computation of the novel 128-bit CLEFIA encryption algorithm and its associated full key expansion. In the existing state of the art only the 128-bit key schedule is supported, given the needed modification to the CLEFIA Feistel network. This work shows that with a small area cost and with no performance impact, full key expansion can be supported. This is achieved by using addressable shift registers, available in modern FPGAs, and adaptable scheduling, allowing to compute the 4 and 8 branch CLEFIA Feistel network within the same structure. The obtained experimental results suggest that throughputs above 1 Gbps can be achieved with a low area cost, while achieving efficiency metrics above those of the restricted state of the art.