Hardware Design Space Exploration with a New Dimension -- IP Protection Robustness

Design space exploration (DSE) is now an important phase of the SoC design process, in order to realize high-efficiency design. In conventional DSE, design metrics such as speed, power and area are extensively used to evaluate various design options. As IP-reuse is widely adopted, protection of hardware IPs has been paid more and more attention at advanced design processes. This paper considers IP protection as a new dimension of DSE. The approach analytically models power consumption, resource usage, execution time and IP protection robustness of hardware designs, and formulates the expanded multi-objective DSE as a constrained optimization problem. The resultant design from solving the optimization problem achieves trade-offs between design performance and IP protection robustness. The approach is validated on three application kernels, demonstrating the capability of the approach in finding optimized designs, which actually locates in the Pareto frontier of the design space.