Reusable SystemVerilog-UVM design framework with constrained stimuli modeling for High Energy Physics applications

A system-level design framework based on SystemVerilog and the standard Universal Verification Methodology is a valuable tool to handle system complexity, evaluate multiple system architectures and achieve best design optimization through the concurrent contribution of multiple designers. This paper is focused on the implementation of such a platform for HEP applications. The specific target are next generation pixel readout integrated circuits for the High Luminosity-Large Hadron Collider at CERN, and the work is performed in the framework of the RD53 and CHIPIX65 collaborations. Thanks to the innovative verification methodology used, the environment features high flexibility and reusability of components. The framework enables designers to simulate and verify multiple DUTs and architectures, which can be described at different abstraction levels (e.g. Transaction Level, RTL,..), in an automated fashion. Constrained and configurable modeling of a wide set of stimuli is provided and statistics on chip performance are collected in order to guide design choices at different stages of the flow. This work is focused on the evaluation of alternative strategies for sharing buffering resources, which are limited in the application due to the impact on area and power consumption. Simulation results are reported for two possible configurations (i.e. sharing within 2×2 or 4×4 pixels) in terms of buffer occupancy.