• DocumentCode
    3677848
  • Title

    Design, Analysis and Optimization to Mount Different Logic Families in a Single IC

  • Author

    Anurag Kumar Sisodia;Piyush Kumar;Deepak Punetha

  • Author_Institution
    Dept. of Electron. &
  • fYear
    2015
  • fDate
    5/1/2015 12:00:00 AM
  • Firstpage
    388
  • Lastpage
    391
  • Abstract
    The Paper report describes the designing, analysis and optimization of different logic family. A logic gate integrated circuit is an idealized or physical device that using for implements a Boolean function. An IC is an arrangement of transistor or diode known as electrically control switches. In this paper report various logic family have been analyzed and mount it in an IC. A logic gate is an elementary building block of a digital circuit. In this paper different logic family under NAND logic has been analyzed by their performance in terms of power dissipation, propagation delay, figure of merit and noise margin.
  • Keywords
    "Logic gates","Transistors","Noise","CMOS integrated circuits","Power dissipation","Propagation delay"
  • Publisher
    ieee
  • Conference_Titel
    Advances in Computing and Communication Engineering (ICACCE), 2015 Second International Conference on
  • Print_ISBN
    978-1-4799-1733-4
  • Type

    conf

  • DOI
    10.1109/ICACCE.2015.69
  • Filename
    7306715