MOSFET parasitic capacitance change in non-zero current and voltage bias conditions

Power MOSFETs have been primarily designed for switching applications, in which case they are operated to the best extent possible either at zero drain to source voltage or at zero drain current. Accordingly, datasheets provide parametric information including input, output and reverse parasitic capacitance at zero current level. When used in linear condition however, both drain to source voltage and drain current are non-zero at the same time, leaving open the question of the parasitic capacitance levels. The present paper reports relevant parameter measurements performed on a MOSFET available for linear control within power units on board of satellite. A parasitic capacitance increase by up to one order of magnitude is highlighted for non-zero currents, in particular between drain and source. The pattern has been confirmed by measurements on two additional MOSFETs. The attention of designers is therefore drawn on such feature as parasitic capacitance may significantly affect the performances of their designs, e.g. in terms of feedback control stability or conducted susceptibility for series regulator, or in terms of speed when switching in between zero current and zero voltage conditions.