Electro-thermal characterization of 1.2 kV normally-on SiC JFETs under hard switch fault

In this paper, the robustness of 1.2 kV normally-on SiC JFETs against short circuits is investigated through experimental parametric analysis and three-dimensional thermal model simulation. Particular emphasis is given to the study of short circuits in the wiring outside the power converter, in which case, a large stray inductance is part of the main power loop. This work presents a more accurate and realistic analysis of the subject, absent from relative literature, since stray inductances are usually ignored. A destructive test is performed in order to obtain the short circuit withstand capability and the failure mechanism of the power device. The experimental results reveal that the loss of the gate control is attributed to the punch-through voltage increase with higher temperatures and depends on the gate current and consequently the turn-off gate resistor.