DocumentCode :
3679099
Title :
Logic Debugging of Arithmetic Circuits
Author :
Samaneh Ghandali;Cunxi Yu;Duo Liu;Walter Brown;Maciej Ciesielski
Author_Institution :
Univ. of Massachusetts, Amherst, MA, USA
fYear :
2015
fDate :
7/1/2015 12:00:00 AM
Firstpage :
113
Lastpage :
118
Abstract :
This paper presents a novel diagnosis and logic debugging method for gate-level arithmetic circuits. It detects logic bugs in a synthesized circuit caused by using a wrong gate ("gate replacement" error), which change the functionality of the circuit. The method is based on modeling the circuit in an algebraic domain and computing its algebraic "signature". The location and type of the bug is determined by comparing signatures computed in both directions, using forward (PI to PO) and backward (PO to PI) rewriting. It will also perform automatic correction for the detected bugs. The approach is demonstrated and tested on a set of integer combinational arithmetic circuits.
Keywords :
"Logic gates","Debugging","Computer bugs","Mathematical model","Polynomials","Adders","Integrated circuit modeling"
Publisher :
ieee
Conference_Titel :
VLSI (ISVLSI), 2015 IEEE Computer Society Annual Symposium on
Type :
conf
DOI :
10.1109/ISVLSI.2015.16
Filename :
7309548
Link To Document :
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