A TMR Strategy with Enhanced Dependability Features Based on a Partial Reconfiguration Flow

Reliability is an important concern in many Field Programmable Gate Array (FPGA) based designs, mainly in applications which must be free of faults, and need to be available for long periods of time. Triple Modular Redundancy (TMR) is a well known approach for a system to tolerate possible faults, but a permanent fault in the TMR hardware may diminish the redundancy advantage. In this paper, we present a low cost solution to improve some dependability figures of a TMR system. The methodology comprises a design flow, which is used in the implementation of the proposed Partial Bit stream for Multiple Partitions (PB4MP) mechanism. The strategy allows modules´s relocation in different Reconfigurable Partitions (RPs) using only one bit stream per module, enabling fault prevention and fault removal (recovery) actions. The results show that with a minor increase in the digital design configuration memory, it is possible to improve considerably the TMR availability, reliability and maintainability.