Low-Power and Low-Variability Programmable Delay Element and Its Application to Post-Silicon Skew Tuning

The post-silicon tuning introducing programmable delay elements (PDEs) to mitigate the manufacturing variability on the delay is promising. This work presents a novel PDE based on the channel-length decomposition, and reveals that it contributes to the low-power and low-variability comparing with a conventional inverter-chain-type. In addition, in a model of a clock tree along with the PDEs, we propose a mechanism for post-silicon tuning of a skew between a pair of flip-flops by a multilevel DLL employing our PDEs of multiple delay steps. In experiments, our proposed mechanism provides a high tunability even under the variability of PDE itself. Furthermore, we demonstrate our mechanism can be used for various clock systems by easy extensions.