A Timing Error Mitigation Technique for High Performance Designs

Dynamic flip-flop conversion (DFFC) is a time borrowing method which converts the critical flip-flops into transparent latches to allow timing slacks pass between pipeline stages of given circuits. However, our previous DFFC methods [13] [14] suffer from false error prediction. It means even when there is no setup time violation, our previous method incorrectly issues timing error. In this paper we present an improved DFFC method which consumes less power and unlike previous DFFC methods does not suffer from false errors. Also we investigate the effectiveness of our proposed DFFC method on different benchmarks by considering all existing critical paths, instead of applying our method only to one of critical paths as done in [13][14]. The results show that our proposed method improves maximum allowable frequency 7.54% on average while the previous method in [13] [14] increases maximum allowable frequency 4.24% on average. Furthermore, it consumes on average 19.59 microwatt less power per critical path compared to previous DFFC methods [13][14].