Fast Stimuli Generation for Design Validation of RTL Circuits Using Binary Particle Swarm Optimization

Generating high quality test sequences for complex digital circuits is known to be extremely challenging. In this paper, we introduce a test generation algorithm using Binary Particle Swarm Optimization (BPSO) to generate high-quality test sequences that achieve high branch coverage in short execution times for synthesizable RTL designs. Initially, a global search is conducted using Binary Particle Swarm Optimization which is later supported by a controlled graphical search method to reach target corner cases. The controlled search uses the control-flow graph to provide hints at critical points in the state space to reach hard corner cases. The fast convergence of BPSO allows the proposed method to deliver high coverage while generating short final test sequences. Substantial speedups over the state of the art methods have also been achieved.