Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs

DRAMs are very sensitive to temperature changes as they use capacitors as volatile and leaky bit storage elements. 3D stacking of heterogenous dies provokes more and more challenges, such as high power densities and thermal dissipation, and has a much stronger impact on the retention time of 3D stacked WIDE I/O DRAMs that are placed on top of an MPSoC. Consequently, it is very important to study the temperature behavior of WIDE I/O DRAMs and explore on high-level with advanced modeling how the thermal issues can be mitigated. In this paper, we demonstrate thermal modeling of 3D integrated ICs and we further provide detailed measurements on temperature-dependent bit error rates of WIDE I/O DRAMs based on real silicon (WIOMING chip) and high-level explorations with advanced modeling and tools, such as gem5 (full system-simulator), DRAMSys and DOCEAs Ace Thermal ModelerTM (ATM), to obtain mitigation paths for thermal problems in 3D stacked DRAMs.