DocumentCode :
3679404
Title :
A novel switched-capacitor based partial power architecture for a 20 MHz resonant SEPIC
Author :
Junjian Zhao;Yehui Han
Author_Institution :
Department of Electrical and Computer Engineering, University of Wisconsin-Madison 1415 Engineering Drive, Madison, WI 53706
fYear :
2015
Firstpage :
1442
Lastpage :
1449
Abstract :
This paper presents a new switched-capacitor (SC) based partial power architecture which enhances the performance of resonant dc-dc converters operating at high frequency (HF, 3 MHz-30 MHz) and very high frequency (VHF, above 30 MHz). A wider input and output range, larger voltage conversion ratio, smaller size and excellent transient performance are expected. The prototype comprises of a 20MHz resonant single-ended-primary-inductor-converter (SEPIC) as a regulated stage and a high-efficiency (96.5 %) 200 kHz SC as an unregulated stage. The resonant SEPIC handles 30 % of total the input power while regulates the output using a high bandwidth (170 kHz) ON/OFF PWM control scheme, which enables fast transient responses. The high-efficiency SC processes 70 % of the input power and provides a large voltage conversion ratio. The low energy storage requirements of the proposed converters allow the use of air-core inductors and ceramic capacitors, thereby eliminating magnetic core loss, and short-lived electrolytic capacitors. The power stage of the prototype achieves a peak efficiency of 93.7 % and a power density of 705.86 W/in3 at 93.88 W.
Keywords :
"Voltage control","RLC circuits","MOSFET","Density measurement","Power system measurements","Switching frequency","Computer architecture"
Publisher :
ieee
Conference_Titel :
Energy Conversion Congress and Exposition (ECCE), 2015 IEEE
ISSN :
2329-3721
Electronic_ISBN :
2329-3748
Type :
conf
DOI :
10.1109/ECCE.2015.7309862
Filename :
7309862
Link To Document :
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