• DocumentCode
    3682284
  • Title

    A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system

  • Author

    Shunli Ma;Guangyao Zhou;Jianbing Jiang;Chixiao Chen;Yongzhen Chen;Fan Ye;Junyan Ren

  • Author_Institution
    State Key Laboratory of ASIC and System, Fudan University, Shanghai, 200433, China
  • fYear
    2015
  • Firstpage
    136
  • Lastpage
    139
  • Abstract
    This paper presents an accurate quadrature clock signals with phase calibration for ultra-high speed real-time sampling system. The proposed four-phase clock generator is a phase locked loop (PLL) with a novel quadrature divider which can realize tunable quadrature phase to calibrate variable mismatches. The operating frequency of the proposed quadrature clock can be tuned from 5.5GHz to 7.85GHz which can be used in four-channel time-interleaved sampler. The real-time sampling system achieve 28-31.2GS/s sampling rate. The chip consumes 28mW power with 1.2V supply voltage in TSMC 65 nm CMOS process. The measurements show that the calibration phase can cover ±10°I phase and Q phase mismatch. The phase noise is -115 dBc/Hz@1MHz offset frequency at 6.85GHz center frequency and cycle-to-cycle time RMS jitter is 210fs.
  • Keywords
    "Clocks","Phase measurement","Transmission line measurements","Calibration","Jitter","Voltage-controlled oscillators","Noise measurement"
  • Publisher
    ieee
  • Conference_Titel
    European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st
  • ISSN
    1930-8833
  • Print_ISBN
    978-1-4673-7470-5
  • Type

    conf

  • DOI
    10.1109/ESSCIRC.2015.7313847
  • Filename
    7313847