Analysis and testing on delays with two time frames

We discuss additional delays caused by various variations that may change overall “observed” behavior of circuits. First we analyze functional changes caused by such additional delays on the inputs of each gate in the circuit. We show that unlike stuck-at faults, such additional delays can introduce many more faulty functions on a gate, and we propose a functional delay fault model with two time frames for such changed behaviors caused by additional delays. The fault model can be examined by tester equipments utilizing the scan paths in the chips. As additional delays by variation and other reasons naturally happen in multiple locations simultaneously, there can be exponentially many multiple fault combinations to be considered. It is not at all easy to analyze it with traditional automatic test pattern generation (ATPG) methods which rely on fault dropping with explicit representation of fault lists. So in the second part of the paper, we present an ATPG method based on implicit representation of fault lists which is formulated as part of the SAT problem for ATPG. As faults are represented implicitly, even if numbers of simultaneous faults are exponentially large, we may still be able to successfully perform ATPG processes. Experimental results have shown that even for ISCAS89 large circuits, complete sets of test vectors for all multiple combinations of the proposed functional delay fault are successfully generated in a couple of hours or so.