Design of asynchronous RISC CPU register-file Write-Back queue

This paper presents the comparison results of Area, Performance and Power of FIFO and Data-Queue on a logically determined Null Convention Logic RISC CPU register file Write-Back circuit. A shift register block implemented using Delay-Insensitive techniques operates in a way that is identical to a FIFO. In this paper, we illustrate the architectures of the Delay-Insensitive Asynchronous Data-Queue and FIFO and analyze the characteristics of these circuits. This comparison results can be also used to the other buffering unit of the CPU such as scoreboard for Dynamic scheduling or Cache Controller memory interface circuits.