Design space exploration of row buffer architecture for phase change memory with LPDDR2-NVM interface

Phase change memory (PCM) is an attractive candidate for the future memory, but it still has several limitations to overcome such as write latency and long-term endurance. A large body of literature has been dedicated to solving these problems. However, almost all of the previous studies did not consider an important practical aspect of the PCM - an interface. The LPDDR2-NVM standard interface recently introduced by JEDEC is widely adopted by the manufacturers of commercial PCM these days. The LPDDR2-NVM standard allows a more flexible use of row buffers compared to the conventional DRAM interface. In this paper, we explore the design space of row buffer architecture in the PCM with LPDDR2-NVM interface. The effect of row buffer architecture on memory performance is investigated in terms of unit size and number of RDBs, and its management policy. We use the timing parameters from industry prototype PCM and analyze the result from the perspective of Pareto´s optimum. The experimental results show that a properly-designed row buffer architecture enhances system-level performance up to 44.2% even at the same cost.