Circuit performance optimization for local intra-die process variations using a gate selection metric

Process variations are imposing strong limits to performance of digital circuits at gigascale integration; they are classified in two types: inter-die and intra-die variations. Moreover, intra-die variations, which were ignored in the past, now have become significant. The present work proposes a statistical performance optimization methodology using a gate selection metric to enhance performance of digital integrated circuits in the presence of local intra-die process variations. The gate selection metric allows to select those gates to be re-sized for improving circuit performance at a lower area cost. This selection metric allows to optimize the circuit behavior using Lagrange method. The obtained results on ISCAS benchmark circuits show the benefits of the proposed methodology. The proposed optimization methodology allows to increases yield leading to better revenue.