A time interleaved DAC sharing SAR Pipeline ADC for ultra-low power camera front ends

The growing need for ultra-low power cameras for sensors, surveillance and consumer applications has resulted in significant advances in compressed domain data acquisition from pixel arrays. In this paper we present a novel 64-input Successive Approximation (SAR) Pipeline analog-to-digital converter (ADC) suitable for compressed domain data acquisition in camera front-ends. The proposed architecture features a time interleaved capacitive digital-to-analog converter (DAC) shared between column parallel ADCs for area savings (2.28X); and a shared amplifier stage for power savings (60%). Simulations on a 130nm foundry process shows that the proposed SAR Pipeline ADC draws 31μW at 2MS/s having a target Figure-of-Merit (FOM) of 87fJ/conv. per step at Nyquist rate.