A time-window based approach for dynamic assertions mining on control signals

Different mining approaches have been proposed in the past for automatic generation of assertions. However, in most cases, existing tools generate a set of over-constrained assertions. As a consequence, each assertion in the set is a long formula that describes a very specific behaviour of the design under verification (DUV). Thus, in the effort of covering as much DUV behaviours as possible, these approaches generate a huge amount of assertions with a negative impact on the total time required for their verification. To overcome this drawback, we introduce a dynamic approach that incrementally analyses control signals on DUV execution traces for mining more expressive temporal assertions that better capture the I/O communication protocol. Experimental results show that our approach allows generating a compact set of assertions without penalizing the coverage of DUV behaviours.