A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging

Bias Temperature Instability (BTI) has become a major aging issue for circuit lifetime reliability in deeply scaled CMOS technologies. Due to BTI, circuit delay increases as time progress, which may lead to a timing constraint violation before the end of the expected lifetime. This paper proposes a new sizing approach to mitigate BTI induced delay degradation of digital circuits. The approach is based on the observation that the delay sensitivity to transistor sizing of a digital gate is composed by a nominal delay sensitivity and a delay degradation sensitivity components. By exploiting the differences between these two components, one can size some gates in the critical paths of a circuit, in such way that the delay degradation due to BTI is reduced while the nominal delay remains nearly unchanged. By using our sizing approach, the reduction of delay degradation allows to further extend the lifetime of a circuit with negligible area and power overhead.