A generic clock controller for low power systems: Experimentation on an AXI bus

Today, high performance and low power consumption are important requirements for the embedded SoCs. The variation in transistors characteristics is increasing as CMOS transistors are scaled to nanometer sizes. Indeed, the MIPS per Watt ratio are more and more an important requirement for digital systems. This makes the power consumption constraint a relevant design criterion. This paper illustrates a new architecture based on an asynchronous approach able to easily reduce the power consumption without performance degradation on an existing design. The evaluation results demonstrate the effectiveness of the proposed technique. This new technique can be considered as generic for systems based on busses or NoCs. Experimentation has been done on the industrial AXI bus.