Fast global interconnnect driven 3D floorplanning

Reduction of interconnect length and thus reduction of power dissipation, and improvement of chip-performance is a key benefit of three-dimensional integrated circuits (3D ICs). However, to profit from 3D, carefully planning global interconnects (e.g. buses or wide IO) already at the floorplanning stage is very important. To this end, we present a new global interconnect driven 3D floorplanner which, different from previous work, simultaneously optimizes global interconnect routes, performs TSV placement, and accounts for fixed-outline floorplanning. For our 3D floorplanner, which is based on Simulated Annealing, we introduce an approach that efficiently guides the optimization process towards a valid and low-cost 3D floorplan solution. Experimental results on GSRC benchmarks demonstrate the efficiency of our tool.