A Watt-Class, High-Efficiency, Digitally-Modulated Polar Power Amplifier in SOI CMOS

This paper presents a digitally-controlled polar power amplifier implemented in 0.18 um SOI CMOS technology. The output amplitude is determined by a 10 bit Amplitude Control Word (ACW) which controls 31 unary cells and 5 binary-weighted cells. Each unit cell is designed as a 4-stacked FET amplifier to achieve high power. The Digital Power Amplifier (digital PA) achieves peak power of 31.6 dBm at >65% drain efficiency at 900 MHz. Peak power and efficiency are both the highest reported to date for CMOS digital PAs. For 5 MHz WCDMA uplink signals, the digital PA gives 28.3 dBm average output power at 49.5% average drain efficiency while meeting ACPR requirements.