Title :
A full-chip ESD simulation flow
Author :
Steven S. Poon;Kushal Sreedhar;Chinmay Joshi;Marco Escalante
Author_Institution :
Intel Corporation, M/S RA3-402, 2501 Northwest 229th Avenue, Hillsboro, OR 97124 USA
Abstract :
An ESD simulation flow that has been demonstrated on 14 nm products is described. Due to Moore´s Law, ESD protection devices are having an increasingly large impact on silicon area, power, and capacitance. A number of real-world examples demonstrating how the simulation flow improved these areas are provided.
Keywords :
"Electrostatic discharges","Clamps","Integrated circuit modeling","Capacitance","Integrated circuit interconnections","MOS devices","Resistance"
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2015 37th
DOI :
10.1109/EOSESD.2015.7314767
