• DocumentCode
    3683173
  • Title

    A new full-chip verification methodology to prevent CDM oxide failures

  • Author

    Melanie Etherton;Scott Ruth;James W. Miller;Rishabh Agarwal;Rishi Bhooshan;Maxim Ershov;Meruzhan Cadjan;Yuri Feinberg;Karthik Srinivasan;Norman Chang; Youlin Liao

  • Author_Institution
    Freescale Semiconductor, Inc., 6501 W William Cannon Dr, Austin, TX 78735 (USA)
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    10
  • Abstract
    This paper describes a new full-chip CDM ESD verification method that enables the evaluation of complete integrated circuits (ICs) for CDM risk. We demonstrate that a robust analysis must comprehend millions of locations of driver-receiver (D/R) pairs on an IC, an accurate model of the grid resistance and an adequate representation of the CDM current distribution.
  • Keywords
    "Electrostatic discharges","Resistance","Discharges (electric)","Integrated circuit modeling","Logic gates","Receivers"
  • Publisher
    ieee
  • Conference_Titel
    Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2015 37th
  • Type

    conf

  • DOI
    10.1109/EOSESD.2015.7314811
  • Filename
    7314811
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3683173