Evaluating the impact of spike and flicker noise in phase change memories

This paper presents a simulation-based analysis of spike and flicker noise in a Phase Change Memory (PCM); this investigation is based on HSPICE simulation by taking into account cell-level (with its neighbors) and array-level considerations. State switching phenomena in binary PCM memories are dealt in detail to assess the impact of these two types of noise. It is shown that a lower feature size is of concern for flicker noise in terms of value and percentage variation (while not substantially affecting array-level performance). This paper also shows that spike noise has a radically different behavior: spike noise shows a dependency on the PCM resistance more than the type of state of the PCM. It increases substantially when the amorphous resistance increases and has a nearly constant value when the memory cell is changing to an amorphous state.