• DocumentCode
    3683232
  • Title

    On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks

  • Author

    Jerry Backer;David Hély;Ramesh Karri

  • Author_Institution
    Polytechnic School of Engineering, New York University, Brooklyn, 11201, USA
  • fYear
    2015
  • Firstpage
    29
  • Lastpage
    34
  • Abstract
    The prevalent use of systems-on-chip (SoCs) makes them prime targets for software attacks. Proposed security countermeasures monitor software execution in real-time, but are impractical, and require impractical changes to the internal logic of intellectual property (IP) cores. We leverage the software observability provided by the readily available SoC debug architecture to detect attacks without modifying IP cores. We add hardware components to configure the debug architecture for security monitoring, to store a golden software execution model, and to notify a trusted kernel process when an attack is detected. Our evaluations show that the additions do not impact runtime software execution, and incur 9% area and power overheads on a low-cost processor core.
  • Keywords
    "Software","Instruments","IP networks","Monitoring","Table lookup","Registers"
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on
  • Type

    conf

  • DOI
    10.1109/DFT.2015.7315131
  • Filename
    7315131