Title :
A BIST approach for counterfeit circuit detection based on NBTI degradation
Author :
Puneet Ramesh Savanur;Phaninder Alladi;Spyros Tragoudas
Author_Institution :
Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, 62901, USA
Abstract :
This paper presents a simple BIST enhancement to detect counterfeit circuits which experience aging delays. The approach is based on the NBTI aging factor. HSPICE simulations on 45nm and 65nm technologies using a predictive NBTI degradation model are presented. The results indicate that counterfeit circuits undergone minimal stress are detected consistently in the presence of process variations.
Keywords :
"Stress","Aging","Delays","Logic gates","Built-in self-test","Accuracy","Benchmark testing"
Conference_Titel :
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on
DOI :
10.1109/DFT.2015.7315148
