A feature design framework for hardware efficient neural spike sorting

We propose a feature design framework that considers simultaneously performance and computational complexity. In particular, we incorporate these two metrics, which are very important to many low-energy on-chip applications such as implantable neural interfaces, onto an optimization problem. This allows us to strike a balance between the performance of the signal processing task and the computational complexity of the feature extraction process. Simulation results for neural spike sorting demonstrate that by leveraging proposed design framework, we can construct features that outperform other state-of-the-art, low-complexity feature designs, both in terms of classification error and complexity.