Synthesis of power aware adaptive schedulers for embedded systems using developmental genetic programming

In this paper we present a method of synthesis of adaptive schedulers for real-time embedded systems. We assume that the system is implemented using multi-core embedded processor with low-power processing capabilities. First, the developmental genetic programming is used to generate the scheduler and the initial schedule. Then, during the system execution the scheduler modifies the schedule whenever execution time of the recently finished task occurred shorter or longer than expected. The goal of rescheduling is to minimize the power consumption while all time constraints will be satisfied. We present real-life example as well as some experimental results showing advantages of our method.