Leakage evaluation on power balance countermeasure against side-channel attack on FPGAs

Power leakage through side-channels has been utilized by attackers to recover secret information in embedded cryptographic systems, and various countermeasures have been devised to mitigate this kind of leakage. In hardware systems, examples of such countermeasures include power balance circuits and masked gates. Power balance technologies such as Wave Dynamic Differential Logic (WDDL) aim to balance the power by introducing differential logic. However, the early evaluation effect, which can take advantage of the possible different arrival times for a pair of differential input signals, hampers the strength of the power balance countermeasure. In this paper, we provide a new method to further balance the power of differential signals by manipulating the lower level primitives and applying placement constraints on a Field Programmable Gate Array (FPGA). We use the Advanced Encryption Standard (AES) encryption algorithm as an example to demonstrate the amount of leakage for different implementations. Results show that constraining the differential pair in one LUT does not guarantee power leakage reduction, and placement constraints on state registers are necessary.