Design of binary architecture for Successive Approximation Analog-to-Digital Converter

The design of comparator, 4-bit binary capacitive-array Digital-to-Analog Converter (DAC) and Successive Approximation Register (SAR) for Successive Approximation Analog-to-Digital Converter (SA-ADC) is implemented in this paper. The comparator contains a pre-amplifier followed by a regenerative latch and an SR latch. The capacitive-array DAC itself does the functioning of sample and/or hold (S/H) circuit i.e. an explicit sample and/or hold (S/H) circuit is not required. The binary-weighted capacitor DAC uses a switching technique to charge the capacitors by the charge distribution principle. For low power purpose, the flip flops used in the SAR are set-reset D-flip flops. The main advantage of this SA-ADC architecture is its low power consumption due to inherent S/H operation inside the capacitor DAC. The supply voltage of the circuits is 700mV. The simulation results of a 4bit binary capacitor DAC, SAR and the comparator circuit is shown on 90nm CMOS technology using Tanner EDA Tools.