FPGA implementation of fully pipelined Advanced Encryption Standard

With worldwide communication of the private and confidential data over the computing networks or internet, there is always a chance of threat of data confidentiality, data integrity and also of data availability. Information has become one of the most important assests in growing demand of need to store every single importance of events in everyday of our life. Encipherment is one of the important security mechanism to protect the data from public access. Encryption will convert the data in such a manner that only a person who has special knowledge of reading it can be able to read it. The Advanced Encryption Standard (AES) is considered to be the strongest encryption technique in cryptography. Advanced Encryption Standard (AES) is a symmetric key block cipher which will encrypt as well as decrypt the data block. Advanced Encryption Standard (AES) can be implemented in both software and hardware. As compared to software implementation hardware implementation of AES has an advantage of increased throughput and more security. In this paper we have presented the FPGA based implementation of 128-bit Advanced Encryption Standard (AES) using fully pipelined architecture. Our proposed architecture can deliver higher throughput at both encryption and decryption operations. Xilinx ISE design suite 13.1 is used for design and Spartan-3 for implementation.